| US 7,576,562 B1 | ||
| Diagnosable structured logic array | ||
| Sterling Whitaker, Albuquerque, N. Mex. (US); Lowell Miles, Albuquerque, N. Mex. (US); Jody Gambles, Post Falls, Id. (US); and Gary K. Maki, Coeur D'Alene, Id. (US) | ||
| Assigned to The United States of America as represented by the United States National Aeronautics and Space Administration, Washington, D.C. (US) | ||
| Filed on Jun. 15, 2007, as Appl. No. 11/818,845. | ||
| Claims priority of provisional application 60/815020, filed on Jun. 19, 2006. | ||
| Int. Cl. H03K 19/173 (2006.01) | ||
| U.S. Cl. 326—40 [326/46] | 23 Claims |
| 1. A base cell structure comprising:
a logic unit comprising a plurality of input nodes, a plurality of selection nodes, and an output node;
a plurality of switches coupled to the selection nodes, the switches comprising a plurality of input lines, a selection line
and an output line;
a memory cell coupled to the output node; and
a test address bus and a program control bus coupled to the plurality of input lines and the selection line of the plurality
of switches;
wherein a state on each of the plurality of input nodes is verifiably loaded and read from the memory cell,
wherein the plurality of switches comprise a triad of multiplexers that are coupled to the selection nodes via the output
line of each of the switches.
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