| US 7,576,436 B2 | ||
| Structure of wafer level package with area bump | ||
| Chih-Pin Hung, Kaoshiung (Taiwan) | ||
| Assigned to Advanced Semiconductor Engineering, Inc., Kaohsiung (Taiwan) | ||
| Filed on Nov. 05, 2007, as Appl. No. 11/934,793. | ||
| Application 11/934793 is a continuation in part of application No. 10/904320, filed on Nov. 03, 2004, abandoned. | ||
| Application 10/904320 is a continuation in part of application No. 10/605012, filed on Sep. 01, 2003, granted, now 6,825,568, filed on Jul. 22, 2004. | ||
| Claims priority of application No. 91220267 U (TW), filed on Dec. 13, 2002. | ||
| Prior Publication US 2008/0054460 A1, Mar. 06, 2008 | ||
| Int. Cl. H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01) | ||
| U.S. Cl. 257—778 [257/786; 257/780] | 19 Claims |
| 1. A package structure, comprising:
at least a chip, comprising an active surface and a plurality of bonding pads on the active surface;
a passivation layer covering the active surface of the chip and exposing the bonding pads;
a redistribution layer on the passivation layer and over the bonding pads of the chip, wherein the redistribution layer comprises
at least a dielectric layer and a patterned metal layer, wherein the patterned metal layer comprises a plurality of first
bumping pads and at least a second bumping pad, the first bumping pads are disposed around a periphery of the second bumping
pad, and the patterned metal layer is electrically connected to the bonding pads;
a plurality of first bumps, respectively connected to the first bumping pads; and
at least a second bump, connected to the second bumping pad, wherein a size of the second bumping pad is larger than a size
of one of the first bumping pads.
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