a first semiconductor layer of a first conduction type;

a pillar layer including first semiconductor pillars of the first conduction type and second semiconductor pillars of a second conduction type formed laterally, periodically and alternately on the first semiconductor layer;

a first main electrode electrically connected to the first semiconductor layer;

a semiconductor base layer of the second conduction type formed selectively on a surface of said pillar layer;

a second semiconductor layer of the first conduction type formed selectively on a surface of said semiconductor base layer;

a second main electrode electrically connected to said second semiconductor layer and said semiconductor base layer; and

a control electrode formed along said semiconductor base layer with an insulator interposed therebetween to form a channel between said second semiconductor layer and said first semiconductor pillar,

wherein said first or second semiconductor pillars include a plurality of diffusion layers periodically formed in a third semiconductor layer for a plurality of periods along a depth direction, said plurality of diffusion layers being coupled along the depth direction, a number of said diffusion layers being formed in one of said periods, said third semiconductor layer formed on said first semiconductor layer,

wherein each of said plurality of diffusion layers in one of the periods has a lateral width in a direction substantially perpendicular to said depth direction different from one another, and

wherein an average of said lateral widths of said diffusion layers in one of said periods is made almost equal to that in another one of said periods.