| US 7,576,382 B2 | ||
| Semiconductor integrated device and method of providing shield interconnection therein | ||
| Tsuyoshi Ueno, Tokyo (Japan) | ||
| Assigned to Ricoh Company, Ltd., Tokyo (Japan) | ||
| Filed on Feb. 01, 2006, as Appl. No. 11/344,191. | ||
| Claims priority of application No. 2005-026600 (JP), filed on Feb. 02, 2005. | ||
| Prior Publication US 2006/0192288 A1, Aug. 31, 2006 | ||
| Int. Cl. H01L 27/108 (2006.01); H01L 29/94 (2006.01) | ||
| U.S. Cl. 257—306 [257/393; 438/396; 438/622] | 6 Claims |
| 1. A semiconductor integrated device comprising:
an interconnection pattern to be shielded;
a plurality of interconnection layers having respective shield interconnection patterns formed therein;
a diffusion formed in the substrate;
a first gate oxide film in contact with the diffusion;
a first polysilicon layer formed on the first gate oxide film;
a second gate oxide film formed on the first polysilicon layer; and
a second polysilicon layer formed on the second gate oxide film,
wherein a first one of the shield interconnection patterns is formed in a first one of the interconnection layers, and a second
one of the shield interconnection patterns is formed in a second one of the interconnection layers, and
wherein the second one of the shield interconnection patterns is connected to the first polysilicon layer, and the first one
of the shield interconnection patterns is connected to the diffusion and the second polysilicon layer, so that a parasitic
capacitance between the first polysilicon layer and the second polysilicon layer is added.
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