| US 7,576,014 B2 | ||
| Semiconductor device and manufacturing method thereof | ||
| Takashi Miyake, Tonami (Japan); and Hiroyuki Doi, Tonami (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Nov. 22, 2005, as Appl. No. 11/283,849. | ||
| Claims priority of application No. 2004-339424 (JP), filed on Nov. 24, 2004. | ||
| Prior Publication US 2006/0110935 A1, May 25, 2006 | ||
| Int. Cl. H01L 21/31 (2006.01); H01L 21/469 (2006.01) | ||
| U.S. Cl. 438—778 [438/132; 438/601; 257/E21.592] | 11 Claims |
| 1. A method of manufacturing a semiconductor device including a plurality of wiring layers and a fuse, the fuse being formed
in a layer of the wiring layers, to be cut to modify a circuit configuration, the manufacturing method comprising the steps
of:
forming a first insulating film so as to coat an uppermost wiring layer of the wiring layers and the fuse;
forming a second insulating film on the first insulating film;
forming an opening for the fuse by etching the first and second insulating films; and
forming a third insulating film so as to coat at least the opening;
wherein the second insulating film has blocking capability against penetration of moisture or impurities higher than that
of the first insulating film, and an intrinsic film property of the third insulating film has blocking capability against
penetration of moisture or impurities higher than that of the second insulating film.
|