| US 7,576,013 B2 | ||
| Method of relieving wafer stress | ||
| Jui-Tsen Huang, Taipei (Taiwan) | ||
| Assigned to United Microelectronics Corp., Hsinchu (Taiwan) | ||
| Filed on Jul. 27, 2004, as Appl. No. 10/710,662. | ||
| Prior Publication US 2006/0024921 A1, Feb. 02, 2006 | ||
| Int. Cl. H01L 21/31 (2006.01); H01L 21/469 (2006.01) | ||
| U.S. Cl. 438—761 [257/E21.598; 257/E21.599] | 14 Claims |
| 1. A stress relieving method for a wafer, comprising the steps of:
providing a wafer with a dielectric layer thereon, wherein the wafer is divided into a first area and a second area such that
at least no circuits are formed on the dielectric layer within the first area;
forming a plurality of first openings in the dielectric layer within the first area; and
forming a first material layer over the wafer, wherein the upper surface of the first material layer has pits at locations
directly over the first openings, and the first material layer is a high stress dielectric layer.
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