US 7,575,967 B2
Semiconductor integrated circuit device and a manufacturing method for the same
Naoto Saitoh, Chiba (Japan); and Yuichiro Kitajima, Chiba (Japan)
Assigned to Seiko Instruments Inc., (Japan)
Filed on Oct. 18, 2006, as Appl. No. 11/582,911.
Claims priority of application No. 2005-304002 (JP), filed on Oct. 19, 2005; application No. 2005-331581 (JP), filed on Nov. 16, 2005; and application No. 2006-282725 (JP), filed on Oct. 17, 2006.
Prior Publication US 2007/0085137 A1, Apr. 19, 2007
Int. Cl. H01L 29/72 (2006.01)
U.S. Cl. 438—197  [438/233; 438/265; 438/759] 11 Claims
OG exemplary drawing
 
1. A manufacturing method for a semiconductor device, comprising the steps of:
forming a gate insulating film on a semiconductor substrate layer of a first conductivity type;
forming a gate electrode by depositing a first polycrystalline silicon on the gate insulating film, introducing impurities to the first polycrystalline silicon, and thereafter patterning the first polycrystalline silicon;
forming a first impurity diffusion layer for a low impurity concentration drain of a second conductivity type within the semiconductor layer of the first conductivity type;
forming a second impurity diffusion layer for a high impurity concentration drain of the second conductivity type adjacent to the first impurity diffusion layer, the second impurity diffusion layer having a higher impurity concentration than the first impurity diffusion layer;
forming an interlayer insulating film on the semiconductor substrate layer;
forming a drain extension region having a high thermal conductivity on a surface of the first impurity diffusion layer;
forming a contact hole through the interlayer insulating film and up to the second impurity diffusion layer; and
depositing a wiring metal layer into the contact hole to form therein a drain electrode that is electrically connected to the second impurity diffusion layer and that is disposed apart from and not in contact with the drain extension region.