| US 7,575,965 B2 | ||
| Method for forming large area display wiring by droplet discharge, and method for manufacturing electronic device and semiconductor device | ||
| Hideaki Kuwabara, Kanagawa (Japan); Shunpei Yamazaki, Tokyo (Japan); Shinji Maekawa, Shizuoka (Japan); and Osamu Nakamura, Kanagawa (Japan) | ||
| Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-Ken (Japan) | ||
| Appl. No. 10/579,443 PCT Filed Nov. 29, 2004, PCT No. PCT/JP2004/018076 § 371(c)(1), (2), (4) Date May 15, 2006, PCT Pub. No. WO2005/059990, PCT Pub. Date Jun. 30, 2005. |
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| Claims priority of application No. 2003-403733 (JP), filed on Dec. 02, 2003; and application No. 2003-432083 (JP), filed on Dec. 26, 2003. | ||
| Prior Publication US 2007/0096096 A1, May 03, 2007 | ||
| Int. Cl. H01L 21/84 (2006.01) | ||
| U.S. Cl. 438—151 [438/157; 438/283; 257/59; 257/66] | 17 Claims |
| 1. A method for manufacturing a semiconductor device comprising the steps of:
forming a base layer over a substrate having an insulating surface;
forming an insulating film over the base layer;
forming a mask over the insulating film;
forming a depression by selectively etching the insulating film using the mask;
forming an embedded wiring in the depression by a droplet discharge method;
removing the mask after the step of forming the embedded wiring;
performing a planarization processing to an upper surface of the embedded wiring;
forming a gate insulating film over the embedded wiring; and
forming a semiconductor film over the gate insulating film.
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