| US 7,575,957 B2 | ||
| Leadless semiconductor package and method for manufacturing the same | ||
| Yao-Ting Huang, Kaohsiung (Taiwan); and Chih-Te Lin, Kaohsiung County (Taiwan) | ||
| Assigned to Advanced Semiconductor Engineering, Inc., Kaohsiung (Taiwan) | ||
| Filed on Jun. 03, 2005, as Appl. No. 11/143,676. | ||
| Claims priority of application No. 93119076 A (TW), filed on Jun. 29, 2004. | ||
| Prior Publication US 2005/0287710 A1, Dec. 29, 2005 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 21/00 (2006.01) | ||
| U.S. Cl. 438—123 [257/676; 257/E23.006; 257/E23.049; 257/E23.052; 257/E23.055] | 16 Claims |
| 1. A method for manufacturing a leadless semiconductor package, comprising:
(a) providing a metal plate having an upper surface and a lower surface;
(b) half-etching the lower surface of the metal plate, so as to form a recession;
(c) forming a non-conductive ink in the recession of the metal plate;
(m) grinding the lower surface of the metal plate where the recession is formed and the non-conductive ink, so that the non-conductive
ink does not cover the lower surface of the metal plate;
(d) patterning the upper surface of the metal plate corresponding to the location of the non-conductive ink to form a plurality
of inner leads and a chip pad connected to the inner leads by the non-conductive ink so that the non-conductive ink is between
every two of the inner leads and couples the inner leads to the chip pad;
(e) placing a semiconductor chip on the chip pad;
(f) using a plurality of bonding wires electrically connecting the semiconductor chip to the inner leads; and
(g) forming a molding compound on the inner leads and the non-conductive ink for encapsulating the semiconductor chip and
the bonding wires;
wherein the step (d) is performed after the step (c).
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