US 11,723,291 B2
Intercalated metal/dielectric structure for nonvolatile memory devices
Mauricio Manfrini, Zhubei (BE); Chung-Te Lin, Tainan (TW); Gerben Doornbos, Kessel-Lo (BE); and Marcus Johannes Henricus van Dal, Linden (BE)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Mar. 31, 2021, as Appl. No. 17/218,324.
Application 17/218,324 is a continuation of application No. 16/412,810, filed on May 15, 2019, granted, now 10,971,684.
Claims priority of provisional application 62/752,571, filed on Oct. 30, 2018.
Prior Publication US 2021/0242398 A1, Aug. 5, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H10N 70/00 (2023.01); G11C 13/00 (2006.01); H10B 63/00 (2023.01)
CPC H10N 70/823 (2023.02) [G11C 13/0007 (2013.01); G11C 13/0011 (2013.01); H10B 63/30 (2023.02); H10N 70/021 (2023.02); H10N 70/841 (2023.02); H10N 70/883 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated chip including a memory device, the memory device comprising:
a bottom electrode disposed over a semiconductor substrate;
an upper electrode disposed over the bottom electrode, such that the bottom electrode separates the upper electrode from the semiconductor substrate;
an intercalated metal and dielectric layer stack sandwiched between the bottom electrode and the upper electrode, the intercalated metal and dielectric layer stack comprising a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer; and
a chalcogenide layer over the upper dielectric layer and separating the upper dielectric layer from the upper electrode;
wherein at least one of the upper electrode and the bottom electrode have a first width and at least one of the lower dielectric layer and the upper dielectric layer have a second width that is different from the first width.