US 11,723,282 B2
Magneto-resistive random-access memory (MRAM) devices with self-aligned top electrode via
Wei-Hao Liao, Taichung (TW); Hsi-Wen Tien, Xinfeng Township, Hsinchu County (TW); Chih-Wei Lu, Hsinchu (TW); Pin-Ren Dai, New Taipei (TW); and Chung-Ju Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacuturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 15, 2021, as Appl. No. 17/231,419.
Application 17/231,419 is a division of application No. 16/440,011, filed on Jun. 13, 2019, granted, now 10,985,312.
Prior Publication US 2021/0257546 A1, Aug. 19, 2021
Int. Cl. H10N 50/01 (2023.01); H01F 41/34 (2006.01); H01F 10/32 (2006.01); H10B 61/00 (2023.01); H10N 50/80 (2023.01)
CPC H10N 50/01 (2023.02) [H01F 10/3254 (2013.01); H01F 41/34 (2013.01); H10B 61/00 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A magnetic random access memory (MRAM) device, comprising:
a bottom electrode over a substrate;
a magnetic tunnel junction (MTJ) structure on the bottom electrode;
a top electrode on the MTJ structure;
spacers on sidewalls of the top electrode and the MTJ structure;
a first dielectric layer surrounding the spacers;
a patterned etch stop layer on the first dielectric layer and the spacers;
a second dielectric layer on the patterned etch stop layer; and
a top electrode via embedded in the second dielectric layer and in contact with the top electrode and the patterned etch stop layer, wherein the top electrode via has a lower portion overlapping and in direct contact with a top surface and a sidewall of the patterned etch stop layer and an upper portion in direct contact with a sidewall of the second dielectric layer.