CPC H10B 61/00 (2023.02) [H10N 50/01 (2023.02); H10N 50/80 (2023.02)] | 7 Claims |
1. A semiconductor device, comprising:
a magnetic tunneling junction (MTJ) on a substrate;
a top electrode on the MTJ;
a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ, wherein a top surface of the first IMD layer is even with a top surface of the top electrode; and
a landing pad on the top electrode and the first IMD layer, wherein a sidewall of the landing pad is aligned with a sidewall of the top electrode.
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