CPC H10B 51/20 (2023.02) [H10B 51/30 (2023.02)] | 20 Claims |
1. A method for forming a memory device, comprising:
forming a plurality of word line stacks respectively comprising a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate;
forming a data storage layer along opposing sidewalls of the word line stacks;
forming a channel layer along opposing sidewalls of the data storage layer;
forming an inner insulating layer between inner sidewalls of the channel layer and comprising a first dielectric material;
performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening;
forming an isolation structure filling the isolation opening and comprising a second dielectric material;
performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings; and
forming source/drain contacts in the source/drain openings.
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