US 11,722,141 B1
Delay-locked-loop timing error mitigation
Leo Filippini, Portland, OR (US); Charles Myers, Portland, OR (US); and Adam Lee, Portland, OR (US)
Assigned to Allegro MicroSystems, LLC, Manchester, NH (US)
Filed by Allegro MicroSystems, LLC, Manchester, NH (US)
Filed on Apr. 22, 2022, as Appl. No. 17/660,221.
Int. Cl. H03L 7/095 (2006.01); H03L 7/081 (2006.01)
CPC H03L 7/095 (2013.01) [H03L 7/0812 (2013.01)] 29 Claims
OG exemplary drawing
 
1. A delay-locked-loop (DLL) false-lock detection system comprising:
(a) DLL circuitry configured to receive a reference clock signal, wherein the reference clock signal includes a clock cycle having a period (T), and produce a delay clock signal as a delayed replica of the reference clock signal on a delay line controlled by a delay line control signal to match the clock cycle of the reference clock signal, the DLL circuitry including a phase detector configured to measure a phase difference between the reference clock signal and the delay clock signal, wherein the phase detector is configured to produce up and down pulses for controlling a delay of the delay clock signal on the delay line relative to the reference clock signal;
(b) a test pulse generator configured to produce an output pulse, wherein the output pulse has a pulse width of a single clock period of the reference clock signal;
(c) a reference delay line configured to receive the output pulse from the test pulse generator and the delay line control signal from the DLL circuitry, wherein the reference delay line is configured to produce an output pulse having the same delay as the delay line of the DLL circuitry relative to the reference clock signal;
(d) shift register circuitry including a plurality of (N) serially connected stages, the shift register circuitry configured to receive the output pulse from the test pulse generator and the reference clock signal from the DLL circuitry, each stage respectively producing an output pulse aligned with a different multiple of the clock period of the reference clock signal; and
(e) a plurality of latched comparison circuits corresponding in number (N) to the stages of the shift register circuitry, wherein each latched comparison circuit is configured to receive the output pulse of the reference delay line and an output pulse from a respective stage of the shift register circuitry and to perform a comparison to evaluate whether the received pulses are matched and produce a respective matched-pulse indication when the pulses are matched, wherein the respective matched-pulse indication indicates a locked condition to a respective multiple (1)−(N) of the reference clock signal period (T).