US 11,722,127 B2
Phase interpolator and phase buffer circuit
Yuan-Sheng Lee, Hsinchu (TW); and Yao-Chia Liu, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on Aug. 4, 2022, as Appl. No. 17/880,828.
Claims priority of application No. 110140264 (TW), filed on Oct. 29, 2021.
Prior Publication US 2023/0133933 A1, May 4, 2023
Int. Cl. H03K 5/135 (2006.01); H03K 5/00 (2006.01)
CPC H03K 5/135 (2013.01) [H03K 2005/00052 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A phase interpolator, comprising:
a plurality of phase interpolator circuitries configured to generate an output clock signal from an output node in response to a plurality of phase control bits and a plurality of clock signals,
wherein phases of the plurality of clock signals are different from each other, each of the plurality of phase interpolator circuitries comprises a plurality of phase buffer circuits, each of the plurality of phase buffer circuits is configured to be turned on according to a first bit and a second bit in the plurality of phase control bits, in order to generate a signal component of the output clock signal to the output node according to a corresponding clock signal in the plurality of clock signals, each of the plurality of phase buffer circuits comprises a first resistor, a second resistor, and a plurality of switches and is configured to transmit one of a first voltage and a second voltage to the output node according to the corresponding clock signal, the plurality of switches are coupled between the first resistor and the second resistor, the first voltage is transmitted to the output node via the first resistor and a first group of switches in the plurality of switches, the second voltage is transmitted to the output node via the second resistor and a second group of switches in the plurality of switches, and the first resistor and the second resistor are configured to set a common mode level of the output node.