CPC H01L 29/78696 (2013.01) [H01L 21/02603 (2013.01); H01L 21/30612 (2013.01); H01L 21/30625 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66522 (2013.01); H01L 29/66742 (2013.01); H01L 29/78681 (2013.01)] | 12 Claims |
1. A manufacturing method of a semiconductor device, comprising:
forming a dielectric layer on a semiconductor substrate;
forming an opening penetrating the dielectric layer and exposing a part of the semiconductor substrate;
forming a stacked structure on the dielectric layer, wherein the stacked structure comprises:
a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer;
a sacrificial layer formed on the first semiconductor layer; and
a second semiconductor layer formed on the sacrificial layer;
performing a patterning process for forming at least one fin-shaped structure on the semiconductor substrate, wherein the stacked structure is patterned by the patterning process, and the at least one fin-shaped structure comprises a part of the first semiconductor layer, a part of the sacrificial layer, and a part of the second semiconductor layer; and
performing an etching process to remove the sacrificial layer in the at least one fin-shaped structure, wherein the first semiconductor layer in the at least one fin-shaped structure is etched to become a first semiconductor wire by the etching process, and the second semiconductor layer in the at least one fin-shaped structure is etched to become a second semiconductor wire by the etching process.
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