US 11,721,753 B2
Method of fabricating a transistor
Alexey Kudymov, Ringoes, NJ (US); Linlin Liu, Hillsborough, NJ (US); Xiaohui Wang, East Brunswick, NJ (US); and Jamal Ramdani, Lambertville, NJ (US)
Assigned to POWER INTEGRATIONS, INC., San Jose, CA (US)
Filed by POWER INTEGRATIONS, INC., San Jose, CA (US)
Filed on Jun. 29, 2021, as Appl. No. 17/362,917.
Application 17/362,917 is a continuation of application No. 16/823,591, filed on Mar. 19, 2020, granted, now 11,075,294.
Application 16/823,591 is a continuation of application No. 16/144,631, filed on Sep. 27, 2018, granted, now 10,629,719, issued on Apr. 21, 2020.
Application 16/144,631 is a continuation of application No. 15/628,269, filed on Jun. 20, 2017, granted, now 10,121,885, issued on Nov. 6, 2018.
Application 15/628,269 is a continuation of application No. 15/096,132, filed on Apr. 11, 2016, granted, now 9,722,063, issued on Aug. 1, 2017.
Prior Publication US 2022/0013660 A1, Jan. 13, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/00 (2006.01); H01L 29/778 (2006.01); H01L 29/205 (2006.01); H01L 23/31 (2006.01); H01L 29/40 (2006.01); H01L 23/29 (2006.01); H01L 29/417 (2006.01); H01L 21/3213 (2006.01); H01L 29/66 (2006.01); H01L 29/20 (2006.01); H01L 21/02 (2006.01); H01L 29/51 (2006.01)
CPC H01L 29/7787 (2013.01) [H01L 21/0217 (2013.01); H01L 21/32136 (2013.01); H01L 23/291 (2013.01); H01L 23/3171 (2013.01); H01L 23/3192 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/404 (2013.01); H01L 29/41758 (2013.01); H01L 29/41775 (2013.01); H01L 29/517 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method of fabricating a transistor comprising:
depositing a gate dielectric;
depositing a first passivation layer and a first insulation layer to form a first composite passivation layer, wherein the first passivation layer is disposed between the gate dielectric and the first insulation layer;
forming a gate electrode;
depositing a second passivation layer and a second insulation layer to form a second composite passivation layer, wherein the second passivation layer is disposed between the first insulation layer and the second insulation layer;
forming a first gate field plate disposed between the first insulation layer and the second passivation layer; and
plasma etching at least part of the first composite passivation layer and the second composite passivation layer prior to forming a second gate field plate.