CPC H01L 29/6681 (2013.01) [H01L 21/31116 (2013.01); H01L 21/76224 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] | 20 Claims |
1. A semiconductor device, comprising:
a fin projecting upwardly from a substrate;
a gate stack engaging the fin;
a source/drain (S/D) feature over the fin;
a gate spacer on a sidewall of the gate stack, the gate spacer having a first sidewall in contact with the gate stack and a second sidewall opposing the first sidewall and directly above the S/D feature; and
a dielectric layer on the sidewall of the gate stack and in contact with the gate stack, the dielectric layer being vertically between the fin and the gate spacer,
wherein a largest thickness of the dielectric layer measured laterally is smaller than a thickness of the gate spacer measured laterally between the first and second sidewalls.
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