CPC H01L 29/4234 (2013.01) [B82Y 10/00 (2013.01); G11C 16/0466 (2013.01); H01L 21/0214 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 29/0649 (2013.01); H01L 29/0676 (2013.01); H01L 29/40117 (2019.08); H01L 29/42344 (2013.01); H01L 29/4916 (2013.01); H01L 29/511 (2013.01); H01L 29/512 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 29/66795 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01); H01L 29/7926 (2013.01); H10B 41/40 (2023.02); H10B 43/00 (2023.02); H10B 43/30 (2023.02); H10B 43/40 (2023.02); H10B 43/50 (2023.02)] | 10 Claims |
1. A semiconductor memory device comprising:
a semiconductor substrate;
an oxide-nitride-oxide structure formed over the substrate, the oxide-nitride-oxide structure having a tunnel oxide layer, a blocking oxide layer and a multi-layer charge storing layer formed between the tunnel oxide layer and the blocking oxide layer;
the multi-layer charge storing layer including a first layer and a second layer, the first layer being an oxygen-rich oxynitride layer and the second layer being an oxygen-lean oxynitride layer; and
a gate coupled to the oxide-nitride-oxide structure.
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