	US 11,721,701 B2
	Semiconductor circuit with metal structure and manufacturing method
Jhon Jhy Liaw, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Mar. 22, 2022, as Appl. No. 17/700,853.
Application 16/728,033 is a division of application No. 15/964,216, filed on Apr. 27, 2018, granted, now 10,756,114, issued on Aug. 25, 2020.
Application 17/700,853 is a continuation of application No. 17/001,362, filed on Aug. 24, 2020, granted, now 11,282,859.
Application 17/001,362 is a continuation of application No. 16/728,033, filed on Dec. 27, 2019, granted, now 10,854,635, issued on Dec. 1, 2020.
Claims priority of provisional application 62/611,037, filed on Dec. 28, 2017.
Prior Publication US 2022/0216238 A1, Jul. 7, 2022
Int. Cl. H01L 27/11 (2006.01); H01L 27/118 (2006.01); H01L 23/522 (2006.01); H01L 27/02 (2006.01); H01L 23/532 (2006.01)

CPC H01L 27/11807 (2013.01) [H01L 23/5226 (2013.01); H01L 27/0207 (2013.01); H01L 23/53233 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 2027/11812 (2013.01); H01L 2027/11831 (2013.01); H01L 2027/11837 (2013.01); H01L 2027/11875 (2013.01); H01L 2027/11881 (2013.01); H01L 2027/11887 (2013.01); H01L 2027/11888 (2013.01)]

20 Claims

1. A semiconductor structure, comprising:

a substrate having a first standard cell, a second standard cell, and a third standard cell, wherein the first standard cell includes an inverter that further includes a first gate stack, wherein the second standard cell includes a logic NAND device that further includes a second and third gate stacks, wherein the third standard cell includes a logic NOR device that further includes a fourth and fifth gate stacks, and wherein the first, second, third, fourth and fifth gate stacks are longitudinally oriented in a first direction;

a first dielectric gate stack disposed between the first and second standard cells;

a second dielectric gate stack disposed between the second and third standard cells, wherein the first and the second dielectric gate stacks are dielectric features and are longitudinally oriented in the first direction;

a first metal layer disposed over the first and second dielectric gate stacks, wherein the first metal layer includes a plurality of first metal lines oriented in a second direction being orthogonal to the first direction;

a second metal layer disposed over the first metal layer, wherein the second metal layer includes a plurality of second metal lines oriented in the first direction; and

a third metal layer disposed over the second metal layer, wherein the third metal layer includes a plurality of third metal lines oriented in the second direction,

wherein the first metal lines have a first minimum pitch P₁measured in the first direction,

wherein the second metal lines have a second minimum pitch P₂measured in the second direction,

wherein the third metal lines have a third minimum pitch P₃measured in the first direction, and

wherein the second minimum pitch P₂is greater than the third minimum pitch P₃.