US 11,721,651 B2
Communication between integrated circuit (IC) dies in wafer-level fan-out package
Chi Fung Poon, Sunnyvale, CA (US); Asma Laraba, San Jose, CA (US); and Parag Upadhyaya, Los Gatos, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Sep. 29, 2020, as Appl. No. 17/37,363.
Prior Publication US 2022/0102293 A1, Mar. 31, 2022
Int. Cl. H01L 23/66 (2006.01); H01L 23/538 (2006.01); H01L 25/16 (2023.01)
CPC H01L 23/66 (2013.01) [H01L 23/5386 (2013.01); H01L 25/16 (2013.01); H01L 2224/02379 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic device comprising:
a wafer-level fan-out package comprising:
a first integrated circuit (IC) die comprising a transmitter circuit, the transmitter circuit comprising a serializer circuit configured to receive parallel data, serialize the parallel data, and output serialized data, the transmitter circuit being configured to transmit the serialized data as multiple single-ended data signals;
a second IC die comprising a receiver circuit; and
a redistribution structure comprising physical channels electrically connected to and between the transmitter circuit and the receiver circuit, the transmitter circuit being configured to transmit the multiple single-ended data signals and a differential clock signal through the physical channels to the receiver circuit, the receiver circuit being configured to capture data from the multiple single-ended data signals using a first single-ended clock signal based on the differential clock signal.