CPC G11C 16/12 (2013.01) [G11C 5/063 (2013.01); G11C 11/4074 (2013.01); G11C 16/0483 (2013.01); G11C 16/3427 (2013.01)] | 20 Claims |
1. A memory, comprising:
an array of memory cells; and
a controller for access of the array of memory cells;
wherein, during a programming operation on the array of memory cells, the controller is configured to cause the memory to:
apply a first voltage level to a data line selectively connected to a memory cell of the array of memory cells that is selected for the programming operation;
apply a second voltage level, lower than the first voltage level, to a control gate of a select gate connected between the data line and the memory cell selected for the programming operation while continuing to apply the first voltage level to the data line;
decrease the voltage level applied to the data line from the first voltage level to a third voltage level while continuing to apply the second voltage level to the control gate of the select gate;
after the voltage level of the data line settles to the third voltage level, increase the voltage level applied to the control gate of the select gate from the second voltage level to a fourth voltage level, higher than the third voltage level, while continuing to apply the third voltage level to the data line; and
after increasing the voltage level applied to the control gate of the select gate to the fourth voltage level, apply a programming voltage to a control gate of the memory cell selected for the programming operation.
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