CPC G11C 11/1659 (2013.01) [G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/18 (2013.01); H10B 61/10 (2023.02)] | 20 Claims |
1. A memory device, comprising:
a magnetic tunnel junction (MTJ);
a spin orbit torque (SOT) layer, in contact with a terminal of the MTJ;
a bit line and a write word line, configured to control a first current path across the SOT layer, wherein the bit line is connected to the SOT layer without any switching device in between, and the write word line is selectively connected to the SOT layer through a two-terminal selector; and
a read word line, connected to another terminal of the MTJ without any switching device in between.
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