CPC G11C 7/109 (2013.01) [G11C 5/147 (2013.01); G11C 5/148 (2013.01); G11C 7/1057 (2013.01); G11C 7/1063 (2013.01); G11C 7/1069 (2013.01); G11C 7/1084 (2013.01); G11C 7/1096 (2013.01); G11C 7/12 (2013.01); G11C 8/10 (2013.01)] | 20 Claims |
1. A memory device, comprising:
a local input/output circuit configured to generate a first local write signal based on a first global write signal and a second global write signal, and configured to transmit the first local write signal to a plurality of first bit lines; and
a main input/output circuit comprising:
a first latch configured to generate a first bit write mask signal based on a clock signal; and
a plurality of logic elements configured to generate the first global write signal and the second global write signal based on the clock signal and the first bit write mask signal.
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