US 11,721,374 B2
Control circuit of memory device
He-Zhou Wan, Shanghai (CN); Xiu-Li Yang, Shanghai (CN); Pei-Le Li, Nanjing (CN); and Ching-Wei Wu, Nantou County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); TSMC NANJING COMPANY LIMITED, Nanjing (CN); and TSMC CHINA COMPANY LIMITED, Shanghai (CN)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); TSMC Nanjing Company Limited, Nanjing (CN); and TSMC China Company Limited, Shanghai (CN)
Filed on Jun. 29, 2022, as Appl. No. 17/853,401.
Application 17/853,401 is a continuation of application No. 17/182,655, filed on Feb. 23, 2021, granted, now 11,393,509.
Claims priority of application No. 202110136033.9 (CN), filed on Feb. 1, 2021.
Prior Publication US 2022/0335988 A1, Oct. 20, 2022
Int. Cl. G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 5/14 (2006.01); G11C 8/10 (2006.01)
CPC G11C 7/109 (2013.01) [G11C 5/147 (2013.01); G11C 5/148 (2013.01); G11C 7/1057 (2013.01); G11C 7/1063 (2013.01); G11C 7/1069 (2013.01); G11C 7/1084 (2013.01); G11C 7/1096 (2013.01); G11C 7/12 (2013.01); G11C 8/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a local input/output circuit configured to generate a first local write signal based on a first global write signal and a second global write signal, and configured to transmit the first local write signal to a plurality of first bit lines; and
a main input/output circuit comprising:
a first latch configured to generate a first bit write mask signal based on a clock signal; and
a plurality of logic elements configured to generate the first global write signal and the second global write signal based on the clock signal and the first bit write mask signal.