US 11,721,300 B2
Display apparatus in which gate pulses are outputted sequentially to alternate sides of a gate line
OhJong Kwon, Paju-si (KR); and Geunyoung Kim, Paju-si (KR)
Assigned to LG Display Co., Ltd., Seoul (KR)
Filed by LG Display Co., Ltd., Seoul (KR)
Filed on Dec. 23, 2021, as Appl. No. 17/561,288.
Claims priority of application No. 10-2020-0189795 (KR), filed on Dec. 31, 2020.
Prior Publication US 2022/0208138 A1, Jun. 30, 2022
Int. Cl. G09G 3/36 (2006.01)
CPC G09G 3/3677 (2013.01) [G09G 3/3688 (2013.01); G09G 2300/0857 (2013.01); G09G 2310/0278 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0289 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A display apparatus, comprising:
a display panel having a first non-display area outside a display area;
a gate driver provided in the first non-display area;
a data driver provided in the first non-display area;
a controller for controlling the gate driver and the data driver;
connection lines extended from the gate driver, the connection lines being provided in a first direction; and
gate lines connected to the connection lines, the gate lines being provided in a second direction different from the first direction,
wherein gate pulses supplied from the gate driver to the gate lines through the connection lines are alternately output from a first side and a second side of the gate lines,
the first side and the second side of the gate lines are divided from each other based on a center portion of the gate lines as a boundary,
the gate driver includes:
an odd shift register including odd flip-flops driven in a second side direction from a first side direction of the gate driver;
an even shift register including even flip-flops driven in the first side direction from the second side direction of the gate driver;
a level shifter unit configured to amplify odd shift clocks and even shift clocks, which are sequentially transmitted from the odd shift register and the even shift register, respectively, and sequentially outputting the amplified odd shift clocks and the amplified even shift clocks; and
a buffer unit configured to sequentially output gate pulses amplified by the level shifter unit to the gate lines.