CPC G06F 17/16 (2013.01) [G06F 7/50 (2013.01); G06F 7/523 (2013.01)] | 18 Claims |
1. An operation accelerator, comprising:
a first memory, configured to store a first matrix, wherein the first matrix is an M*N matrix;
a second memory, configured to store a second matrix, wherein the second matrix is an N*K matrix;
an operation circuit connected to the first memory and the second memory, wherein the operation circuit comprises a matrix multiplying circuit; the matrix multiplying circuit comprises M operation groups, each operation group comprises K operation blocks, each operation block comprises N operation units, each operation unit receives two pieces of data respectively from the first memory and the second memory, and the operation unit multiplies the two pieces of data, so that the operation accelerator can perform M*N*K times of multiplication in one clock cycle; M, N, and K are integers greater than 0; and
a storage unit access controller connected to the first memory, the second memory, a third memory, and a controller, wherein the storage unit access controller is configured to: obtain, under control of the controller, the source data of the first matrix and the second matrix, save the source data of the first matrix to the third memory, and save the second matrix to the second memory.
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