US 11,720,512 B2
Unified systems and methods for interchip and intrachip node communication
Richard Dominic Wietfeldt, San Diego, CA (US); Maxime Leclercq, Encinitas, CA (US); and George Alan Wiley, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jun. 30, 2021, as Appl. No. 17/363,407.
Application 17/363,407 is a division of application No. 14/850,104, filed on Sep. 10, 2015, abandoned.
Prior Publication US 2021/0326290 A1, Oct. 21, 2021
Int. Cl. G06F 13/40 (2006.01); G06F 13/38 (2006.01); H04L 43/0817 (2022.01)
CPC G06F 13/4027 (2013.01) [G06F 13/385 (2013.01); G06F 13/4068 (2013.01); H04L 43/0817 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A computing system comprising:
a first integrated circuit (IC) comprising:
a first node comprising a first transmitter and a first receiver;
a first gateway comprising:
a first external interface;
a first status table configured to:
register the first node; and
indicate availability of the first node; and
a first internal interface communicatively coupled to the first node and configured to communicate therebetween;
a second IC comprising:
a second node comprising a second transmitter and a second receiver;
a second gateway comprising:
a second external interface;
a second status table configured to:
register the second node; and
indicate availability of the second node; and
a second internal interface communicatively coupled to the second node and configured to communicate therebetween; and
a bus coupled to the first gateway of the first IC and the second gateway of the second IC and configured to carry signals therebetween.