US 11,720,486 B2
Memory data access apparatus and method thereof
Yen-Ju Lu, Hsinchu (TW); and Chao-Wei Huang, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on Aug. 11, 2020, as Appl. No. 16/990,926.
Claims priority of application No. 108144948 (TW), filed on Dec. 9, 2019.
Prior Publication US 2021/0173772 A1, Jun. 10, 2021
Int. Cl. G06F 12/02 (2006.01); G06F 12/14 (2006.01); G06F 9/30 (2018.01); G06F 13/40 (2006.01); G06F 12/0846 (2016.01)
CPC G06F 12/0246 (2013.01) [G06F 9/30105 (2013.01); G06F 12/0848 (2013.01); G06F 12/1441 (2013.01); G06F 13/4068 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A memory data access method, comprising:
executing a memory read instruction, wherein the memory read instruction comprises a memory address;
determining that access of the memory address in the cache memory is missed;
after determining that access of the memory address in the cache of memory is missed, determining that the memory address is within a pre-determined memory address range, wherein the pre-determined memory address range corresponds to a data access amount;
reading a data block corresponding to the data access amount from the memory address of a memory;
selecting a cache way from a plurality of cache ways of the cache memory;
dividing the data block into a plurality of line data, wherein size of each line data is the same as size of a cache line; and
writing at least one of the plurality of line data into the selected cache way.