CPC G06F 12/023 (2013.01) [G11C 7/1006 (2013.01); G11C 7/1039 (2013.01); G11C 7/22 (2013.01); G11C 8/10 (2013.01); H05K 999/99 (2013.01); G06F 2212/2024 (2013.01); G11C 2207/107 (2013.01)] | 20 Claims |
1. A dynamic random access memory (DRAM) device comprising:
a memory core having an array of DRAM cells;
a register to store first data in response to a register-write command;
a command/address interface that receives commands and addresses, the command/address interface to receive the register-write command and the first data, and then, after the first data has been stored in the register, to receive first and second memory access commands;
a data interface to receive second data in response to the second memory access command, wherein the data interface does not receive the first data; and
control circuitry to write the first data from the register to the memory core in response to the first memory access command and to write the second data from the data interface to the memory core in response to the second memory access command.
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