CPC G06F 9/3806 (2013.01) [G06F 12/0864 (2013.01); G06F 12/0875 (2013.01); G06F 2212/452 (2013.01); Y02D 10/00 (2018.01)] | 20 Claims |
1. An instruction processing apparatus, comprising:
an instruction fetch unit, adapted to obtain an instruction based on an instruction address of a program counter;
an execution unit, coupled to the instruction fetch unit, and adapted to execute the instruction;
an instruction cache, adapted to store instruction content accessed by using the instruction address, wherein the instruction cache maps data blocks in a memory based on a multi-way set-associative structure and comprises a plurality of cache lines; and
an access control unit, coupled between the instruction fetch unit and the instruction cache, and adapted to read the plurality of cache lines respectively by using a plurality of data channels, and select a cache line from the plurality of cache lines by using a plurality of selection channels, to obtain the instruction, wherein
the access control unit comprises a path prediction unit, wherein the path prediction unit is enabled based on a signal indicating that energy in the instruction processing apparatus is below a critical point, and wherein the path prediction unit is adapted to:
determine a type of the instruction,
obtain, based on the determined type of the instruction, path prediction information corresponding to the instruction address, and
enable at least one data channel and/or at least one selection channel based on the path prediction information.
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