US 11,720,360 B2
DSB operation with excluded region
Jeff Gonion, Campbell, CA (US); John H. Kelm, Belmont, CA (US); James Vash, San Ramon, CA (US); Pradeep Kanapathipillai, Santa Clara, CA (US); Mridul Agarwal, Saratoga, CA (US); Gideon N. Levinsky, Cedar Park, TX (US); Richard F. Russo, Saratoga, CA (US); and Christopher M. Tsay, Austin, TX (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Sep. 8, 2021, as Appl. No. 17/469,504.
Claims priority of provisional application 63/077,385, filed on Sep. 11, 2020.
Prior Publication US 2022/0083338 A1, Mar. 17, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 12/02 (2006.01); G06F 12/0875 (2016.01); G06F 9/38 (2018.01)
CPC G06F 9/30087 (2013.01) [G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 9/30101 (2013.01); G06F 9/3834 (2013.01); G06F 12/0238 (2013.01); G06F 12/0875 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a plurality of processors, wherein the plurality of processors each include one or more registers programmable to define an exclusion region of a memory address space, and wherein the plurality of processors are communicatively coupled, wherein:
a first processor of the plurality of processors is configured to issue a first data barrier operation request responsive to executing a data barrier instruction;
a second processor of the plurality of processors is configured to, based on receiving the first data barrier operation request from the first processor:
ensure that outstanding load/store operations executed by the second processor that are directed to addresses outside of the exclusion region have been completed; and
respond to the first processor that the first data barrier operation request is complete at the second processor, even in the case that one or more load/store operations directed to addresses within the exclusion region are outstanding and not complete when the second processor responds that the first data barrier operation request is complete.