CPC G06F 9/30087 (2013.01) [G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 9/30101 (2013.01); G06F 9/3834 (2013.01); G06F 12/0238 (2013.01); G06F 12/0875 (2013.01)] | 20 Claims |
1. A system, comprising:
a plurality of processors, wherein the plurality of processors each include one or more registers programmable to define an exclusion region of a memory address space, and wherein the plurality of processors are communicatively coupled, wherein:
a first processor of the plurality of processors is configured to issue a first data barrier operation request responsive to executing a data barrier instruction;
a second processor of the plurality of processors is configured to, based on receiving the first data barrier operation request from the first processor:
ensure that outstanding load/store operations executed by the second processor that are directed to addresses outside of the exclusion region have been completed; and
respond to the first processor that the first data barrier operation request is complete at the second processor, even in the case that one or more load/store operations directed to addresses within the exclusion region are outstanding and not complete when the second processor responds that the first data barrier operation request is complete.
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