US 11,720,359 B2
Large data read techniques
Qing Liang, Boise, ID (US); and Nadav Grosz, Broomfield, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 21, 2021, as Appl. No. 17/558,140.
Application 17/558,140 is a continuation of application No. 16/565,021, filed on Sep. 9, 2019, granted, now 11,210,093.
Claims priority of provisional application 62/861,144, filed on Jun. 13, 2019.
Claims priority of provisional application 62/830,935, filed on Apr. 8, 2019.
Prior Publication US 2022/0113970 A1, Apr. 14, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 9/30 (2018.01); G06F 9/48 (2006.01); G06F 3/06 (2006.01); G06F 12/1009 (2016.01)
CPC G06F 9/30047 (2013.01) [G06F 3/0613 (2013.01); G06F 3/0617 (2013.01); G06F 3/0646 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 9/4806 (2013.01); G06F 12/1009 (2013.01); G06F 2212/7201 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for reading data from a NAND memory device, the method comprising:
receiving a read command from a host device, the read command including a first address;
determining that the read command includes a flag matching a pre-specified value;
responsive to the flag matching the pre-specified value:
identifying a parameter list length in the read command;
receiving, from the host device, a set of additional addresses in a second message from the host device, a size of the set of additional addresses corresponding to the parameter list length; and
responsive to receiving, from the host device, the set of additional addresses, reading data from a NAND array at the first address and from each address of the set of additional addresses.