CPC G06F 7/50 (2013.01) [H03M 1/12 (2013.01)] | 10 Claims |
1. A temperature compensation circuit for a neural network computing-in-memory array, configured to perform temperature compensation on the neural network computing-in-memory array composed of N-type floating-gate devices, wherein the temperature compensation circuit comprises a reference array composed of two rows of N-type floating-gate devices for storing weights, a current subtractor circuit and an I-V conversion resistor R1;
the two rows of N-type floating-gate devices for storing weights respectively comprise n N-type floating-gate devices MR1+-MRn+ and n N-type floating-gate devices MR1-MRn−; in the reference array, gates of the n N-type floating-gate devices MR1+-MRn+ are connected to a same fixed voltage VGS, drains are connected to a same fixed voltage VDS, and sources are connected with each other and to a fixed voltage VS and connected into a positive input end of the current subtractor circuit; in the reference array, gates of the n N-type floating-gate devices MR1− MRn− are connected to the same fixed voltage VGS, drains are connected to the same fixed voltage VDS, and sources are connected with each other and to the fixed voltage VS and connected into a negative input end of the current subtractor circuit;
an output end of the subtractor circuit is connected to one end of the I-V conversion resistor R1, and connected through a voltage buffer into a reference end of an analog-to-digital converter (ADC) connected with the computing-in-memory array; the other end of the I-V conversion resistor R1 is grounded; and
the I-V conversion resistor R1 has same parameters as an I-V conversion resistor R0 in a readout circuit of the computing-in-memory array.
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