US 11,720,261 B2
Transferring memory system data to a host system
Qing Liang, Boise, ID (US); Nadav Grosz, Broomfield, CO (US); Jonathan S. Parry, Boise, ID (US); and Deping He, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 10, 2020, as Appl. No. 16/989,596.
Prior Publication US 2022/0043586 A1, Feb. 10, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0625 (2013.01) [G06F 3/0623 (2013.01); G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first memory array associated with a first degree of volatility,
a second memory array associated with a second degree of volatility that is greater than the first degree of volatility,
an interface configured to couple the apparatus with a host system, and
a controller coupled with the first memory array, the second memory array, and the interface, wherein the controller is configured to cause the apparatus to:
receive a command from the host system associated with entering a reduced power mode;
transmit, via the interface and based at least in part on the command associated with entering the reduced power mode, information associated with a processing capability of the apparatus and stored in the second memory array to the host system, wherein the information comprises tightly-coupled memory (TCM) information, inter-process communication (IPC) information, redundant array information, a firmware mapping table, or a combination thereof;
enter the reduced power mode after transmitting the information to the host system;
exit the reduced power mode; and
receive, via the interface and based at least in part on exiting the reduced power mode, the information.