CPC G06F 1/28 (2013.01) [G06F 13/4282 (2013.01)] | 17 Claims |
1. A voltage regulator comprising:
a processor;
a register bank coupled to the processor; and
a logic block coupled to the processor and to the register bank, the logic block includes a frame decision maker, a first decoder and a second decoder, the frame decision maker configured to receive frames and configured to generate an interpret frame from a first one of the frames, and the processor, based on the interpret frame, configured to:
activate a set of protocol registers storing protocol information corresponding to one of a first protocol or a second protocol;
enable configuration settings in the register bank corresponding to one of the first protocol or the second protocol; and
enable one of the first decoder and the second decoder to decode a command in the first frame, wherein each of the first decoder and the second decoder are configurable to decode a frame compliant with the first protocol and a frame compliant with the second protocol for high speed serial interface (HSSI).
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