US 11,720,159 B2
Unified bus architecture for a voltage regulator
Venkatesh Wadeyar, Bengaluru (IN); Vikas Lakhanpal, Bengaluru (IN); and Preetam Charan Anand Tadeparthy, Bengaluru (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jun. 30, 2020, as Appl. No. 16/917,423.
Claims priority of application No. 201941026259 (IN), filed on Jul. 1, 2019.
Prior Publication US 2021/0004072 A1, Jan. 7, 2021
Int. Cl. G06F 1/28 (2006.01); G06F 13/42 (2006.01)
CPC G06F 1/28 (2013.01) [G06F 13/4282 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A voltage regulator comprising:
a processor;
a register bank coupled to the processor; and
a logic block coupled to the processor and to the register bank, the logic block includes a frame decision maker, a first decoder and a second decoder, the frame decision maker configured to receive frames and configured to generate an interpret frame from a first one of the frames, and the processor, based on the interpret frame, configured to:
activate a set of protocol registers storing protocol information corresponding to one of a first protocol or a second protocol;
enable configuration settings in the register bank corresponding to one of the first protocol or the second protocol; and
enable one of the first decoder and the second decoder to decode a command in the first frame, wherein each of the first decoder and the second decoder are configurable to decode a frame compliant with the first protocol and a frame compliant with the second protocol for high speed serial interface (HSSI).