US 11,719,648 B2
Method for smart conversion and calibration of coordinate
Iyun Leu, Hsinchu (TW)
Assigned to ELITE SEMICONDUCTOR INC., Zhudong Town (TW)
Filed by ELITE SEMICONDUCTOR INC., Zhudong Town (TW)
Filed on Apr. 16, 2021, as Appl. No. 17/233,202.
Application 17/233,202 is a continuation of application No. 62/559,784, filed on Sep. 18, 2017.
Prior Publication US 2021/0231579 A1, Jul. 29, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G01N 21/95 (2006.01); H01L 21/66 (2006.01); G06T 7/00 (2017.01); G01N 21/88 (2006.01); G06F 30/398 (2020.01); G06F 30/3323 (2020.01)
CPC G01N 21/9501 (2013.01) [G01N 21/8851 (2013.01); G06F 30/3323 (2020.01); G06F 30/398 (2020.01); G06T 7/001 (2013.01); H01L 22/12 (2013.01); H01L 22/20 (2013.01); G01N 2021/8861 (2013.01); G01N 2021/8864 (2013.01); G01N 2021/8874 (2013.01); G06T 2207/30148 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A method for smart conversion and calibration of coordinate by means of a coordinate conversion and calibration system including a data processing apparatus and a storage apparatus, the method comprising coordinate deviation calibration:
providing an integrated circuit design layout file, the integrated circuit design layout file has a plurality of circuit layout patterns and is stored into the storage apparatus;
processing a wafer fabrication process, a semiconductor manufacturing fab forms the plurality of circuit layout patterns on the wafer according to the integrated circuit design layout file;
processing a wafer defect scan and inspection by a defect inspection tool to obtain a defect inspection data, the data processing apparatus transforms the defect inspection data into a defect text and image data file and stores into the storage apparatus, wherein the defect text and image data file includes a plurality of defect data on the wafer, and each of the defect data at least includes a defect coordinate, a defect size, a defect area and a defect intensity value of a defect contour;
adjusting dimension units of the defect size, a defect coordinate and the circuit layout pattern to be the same dimension unit by the data processing apparatus;
converting the defect contour onto a correct defect coordinate (X2, Y2) of the circuit layout pattern for a real-time pattern match by the data processing apparatus;
executing a coordinate deviation calibration by the data processing apparatus, which includes:
performing a manual pattern match by a user to measure a coordinate deviation calibration value (X2′-X2, Y2′-Y2), by adjusting the dimension unit of the displayed defect layout pattern and the defect contour to be the same, and manually marking a defect contour location to a corresponding location in the circuit layout pattern as a new coordinate location (X2′, Y2′), wherein the step of the manual pattern match includes manually processing a coordinate deviation distance from a defect layout pattern coordinate to an actual defect layout pattern coordinate to map the defect contour on a monitor screen, then the defect layout pattern and the defect contour are aligned manually with a setting coordinate value, wherein if the correct defect coordinate (X2, Y2) in a converted defect layout pattern is not at the same location with the new coordinate location (X2′, Y2′) in the defect contour, the coordinate deviation calibration must be performed to calibrate the new coordinate location (X2′, Y2′), and wherein the coordinate deviation calibration is accomplished via a mouse cursor manually marking the defect coordinate corresponding to the location in the circuit layout pattern as the new coordinate location (X2′, Y2′);
obtaining the coordinate deviation calibration value (X2′-X2, Y2′-Y2) by the data processing apparatus, the coordinate deviation calibration value (X2′-X2, Y2′-Y2) includes an average coordinate precision value and a coordinate precision standard deviation value for X-axis and Y-axis, the average coordinate precision value and the coordinate precision standard deviation value are calculated via a statistical analysis;
introducing the average coordinate precision value and the coordinate precision standard deviation value into the coordinate conversion and calibration system in order to overlap or map a defect coordinate (X1, Y1) to the new coordinate location (X2′, Y2′) based on the coordinate deviation calibration value (X2′-X2, Y2′-Y2) after the coordinate deviation calibration;
executing an overlapping procedure by the data processing apparatus, the data processing apparatus retrieves sequentially the defect coordinate, the defect size and the defect area of the defect contour from the defect text and image data file, and overlaps the defect size and the defect area onto the coordinate deviation calibration value at a coordinate deviation area of the circuit layout pattern based on the corresponding defect coordinate after the conversion and calibration of coordinate; and
executing a Critical Area Analysis (CAA) by the data processing apparatus, based on the overlapping of the calibrated defect size and defect area onto the mapped circuit layout pattern, the data processing apparatus uses the CAA to analyze a critical area within the coordinate deviation area for each of the defects, and decides a Killer Defect Index (KDI) value.