| US 7,574,687 B1 | ||
| Method and system to optimize timing margin in a system in package module | ||
| Sergio Camerlo, Cupertino, Calif. (US); and Wheling Cheng, Palo Alto, Calif. (US) | ||
| Assigned to Cisco Technology, Inc., San Jose, Calif. (US) | ||
| Filed on Jan. 03, 2006, as Appl. No. 11/325,027. | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—16 [716/6; 716/13] | 5 Claims |
| 1. A method for optimizing timing margin of a clock in a System-in-Package (SiP) module, the method comprising:
generating timing dependent signal from a controller circuit device mounted on a SiP module;
transmitting the timing dependent signal to a serpentine trace on a Printed Circuit Board (PCB) to delay the timing dependent
signal; and
transmitting the delayed timing dependent signal to a controlled circuit device mounted on the SiP module.
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