| US 7,574,685 B1 | ||
| Method, system, and article of manufacture for reducing via failures in an integrated circuit design | ||
| Xiaopeng Dong, San Jose, Calif. (US); Inhwan Seo, Fremont, Calif. (US); William Kao, Fremont, Calif. (US); David C. Noice, Palo Alto, Calif. (US); and Gary Nunn, Los Gatos, Calif. (US) | ||
| Assigned to Cadence Design Systems, Inc., San Jose, Calif. (US) | ||
| Filed on Apr. 24, 2007, as Appl. No. 11/739,622. | ||
| Claims priority of provisional application 60/794650, filed on Apr. 24, 2006. | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—11 [716/5] | 24 Claims |
| 1. A method for locating via fills comprising:
establishing a window to check for a via filling parameter within a particular section of a design;
determining whether the via filling parameter within the window meets a via filling parameter requirement;
adding by a processor one or more additional via fills if the via filling parameter requirement is not met, wherein the act
of adding the one or more additional via fills comprises adding additional vias to the design until a density requirement
of cuts for the window has been met; and
storing the added one or more additional via fills in a volatile or non-volatile computer readable medium or displaying the
added one or more additional via fills on a display device.
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