| US 7,574,616 B2 | ||
| Memory device having a power down exit register | ||
| Richard M. Barth, Palo Alto, Calif. (US); Ely K. Tsern, Los Altos, Calif. (US); Craig E. Hampel, San Jose, Calif. (US); Frederick A. Ware, Los Altos Hills, Calif. (US); Todd W. Bystrom, Sunnyvale, Calif. (US); Bradley A. May, San Jose, Calif. (US); and Paul G. Davis, San Jose, Calif. (US) | ||
| Assigned to Rambus Inc., Los Altos, Calif. (US) | ||
| Filed on Sep. 17, 2004, as Appl. No. 10/944,320. | ||
| Application 10/944320 is a continuation of application No. 09/685014, filed on Oct. 05, 2000, granted, now 6,842,864. | ||
| Application 09/685014 is a continuation of application No. 09/038358, filed on Mar. 10, 1998, granted, now 6,154,821. | ||
| Prior Publication US 2005/0060487 A1, Mar. 17, 2005 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 1/26 (2006.01) | ||
| U.S. Cl. 713—320 [711/105; 711/167] | 41 Claims |
| 1. An integrated circuit memory device comprising:
an interface to receive an instruction to exit a power down mode;
an array of dynamic random access memory cells; and
a register to store a value representative of a period of time to elapse between exiting from the power down mode and a time
at which the integrated circuit memory device is capable of receiving a command that specifies an access to the array of dynamic
random access memory cells.
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