| US 7,574,555 B2 | ||
| Memory system having daisy chained memory controllers | ||
| Ofer Porat, Westborough, Mass. (US); Brian K. Campbell, Cedar Park, Tex. (US); Brian D. Magnuson, Somerville, Mass. (US); and Stephen Scaringella, Holliston, Mass. (US) | ||
| Assigned to EMC Corporation, Hopkinton, Mass. (US) | ||
| Filed on Mar. 18, 2005, as Appl. No. 11/83,571. | ||
| Prior Publication US 2006/0212622 A1, Sep. 21, 2006 | ||
| Int. Cl. G06F 12/00 (2006.01); G06F 12/02 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01) | ||
| U.S. Cl. 711—105 [711/1] | 2 Claims |
| 1. A data storage system having an interface for coupling a host computer/server to a bank of disk drives, such interface
having a pair of redundant packet switching networks, each one being coupled to front end controllers, back end controllers
and a cache memory, such cache memory, comprising:
a pair of bi-directional ports, each one being connected to a corresponding one of the pair of packet switching networks,
each one of the ports providing address and read/write control signals to the memory system;
a plurality of sets of memory modules;
a plurality of memory controllers, each one of the memory controllers being coupled to a corresponding one of the plurality
of sets of memory modules;
wherein each one of the memory controllers includes an arbiter coupled to the corresponding one of the plurality of sets of
memory modules, such arbiter being coupled to the pair of bi-directional ports to determine which one of the pair of bi-directional
ports is to have access to the one of the sets of memory modules coupled to such one of the arbiters; and
wherein the memory controllers are interconnected in a daisy chain arrangement to the ports, a first one of the memory controllers
in the daisy chain being coupled to a first one of the pair of ports and a last one of the memory controllers in the daisy
chain being coupled to a second one of the pair of ports; and
wherein a signal path for the address and read/write control signals from the first one of the pair of ports through the controllers
is in a direction opposite to a signal path for the address and read/write control signals from the second one of the pair
of ports through the controllers.
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