| US 7,574,468 B1 | ||
| Digital signal processor having inverse discrete cosine transform engine for video decoding and partitioned distributed arithmetic multiply/accumulate unit therefor | ||
| Jitendra Rayala, San Jose, Calif. (US) | ||
| Assigned to VeriSilicon Holdings (Cayman Islands) Co. Ltd., Santa Clara, Calif. (US) | ||
| Filed on Mar. 18, 2005, as Appl. No. 11/83,575. | ||
| Int. Cl. G06F 17/14 (2006.01) | ||
| U.S. Cl. 708—402 | 16 Claims |
| 1. A distributed arithmetic multiply/accumulate (MAC) unit for computing inverse discrete cosine transformations, comprising:
a first pipeline stage of said distributed arithmetic MAC configured to perform dot products on received sequential input
data, wherein row transformations are performed initially and column transformations are performed subsequent to said row
transformations; and
a second pipeline stage of said distributed arithmetic MAC coupled to said first pipeline stage and configured to compute
additions and subtractions of said dot products to yield sequential output data,
wherein said distributed arithmetic MAC unit has a 12-bit precision.
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