| US 7,573,767 B2 | ||
| Semiconductor memory device | ||
| Kazuhiko Kajigaya, Tokyo (Japan) | ||
| Assigned to Elpida Memory, Inc., Tokyo (Japan) | ||
| Filed on Aug. 06, 2007, as Appl. No. 11/882,827. | ||
| Claims priority of application No. 2006-217575 (JP), filed on Aug. 09, 2006. | ||
| Prior Publication US 2008/0037356 A1, Feb. 14, 2008 | ||
| Int. Cl. G11C 7/02 (2006.01) | ||
| U.S. Cl. 365—207 [365/230.03] | 10 Claims |
| 1. A semiconductor memory device in which a memory cell array including a plurality of memory cells formed at intersections
between a plurality of word lines and a plurality of bit lines, comprising:
a plurality of unit blocks into which the memory cell array is divided;
a plurality of rows of sense amplifiers arranged at one end and the other end of the plurality of bit lines in said unit block
and each including a plurality of sense amplifiers for amplifying data of the memory cells for each bit line pair;
switch means for switching a connection state between said unit block and said row of sense amplifiers attached to said unit
block; and
control means for controlling said switch means so as to form a transfer path from said row of sense amplifiers attached to
a predetermined said unit block leading to said row of sense amplifiers as a saving destination not attached to the predetermined
said unit block, in a state in which said row of sense amplifiers attached to the predetermined said unit block is controlled
to be used as a cache memory, for performing a saving operation so that the stored data in the cache memory is saved in said
row of sense amplifiers as the saving destination through the transfer path, and for performing a write back operation so
that the stored data is written back into the cache memory through the transfer path in reverse direction.
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