| US 7,573,765 B2 | ||
| Semiconductor memory device | ||
| Hideyoshi Takai, Tokyo (Japan); and Takamichi Kasai, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Aug. 28, 2007, as Appl. No. 11/846,026. | ||
| Claims priority of application No. 2006-237651 (JP), filed on Sep. 01, 2006. | ||
| Prior Publication US 2008/0056050 A1, Mar. 06, 2008 | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—201 [365/185.09; 365/233.5] | 19 Claims |
| 1. A semiconductor memory device comprising:
an internal address generation circuit which generates an internal signal based on input address data;
a first internal address control signal generation part which generates a first internal address control signal and includes
a function for fixing said first internal address control signal at a predetermined level with the elapse of a fixed period
of time;
a second internal address control signal generation part which generates a second internal address control signal according
to an input of a predetermined command, said second internal address control signal instructing said internal address generation
circuit to generate said internal address signal based on said address data; and
an internal address control signal selection circuit which selects according to an input test mode signal either said first
internal address control signal or said second internal address control signal, said internal address control signal selection
circuit also including an OR gate transistor which transmits to said internal address generation circuit, and at the time
of a test mode said internal address control signal selection circuit selects said second internal address control signal
and transmits to said internal address generation circuit.
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