| US 7,573,760 B2 | ||
| Integrated circuit for sampling a sequence of data packets at a data output | ||
| Christian Sichert, Munich (Germany); Rainer Bartenschlager, Kaufbeuren (Germany); Franz Freimuth, Munich (Germany); and Jens Polney, Munich (Germany) | ||
| Assigned to Qimonda AG, Munich (Germany) | ||
| Filed on Sep. 12, 2007, as Appl. No. 11/854,463. | ||
| Claims priority of application No. 10 2006 042 858 (DE), filed on Sep. 13, 2006. | ||
| Prior Publication US 2008/0061852 A1, Mar. 13, 2008 | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—198 [365/230.01; 365/189.17; 365/193; 365/230.03; 365/230.04] | 24 Claims |
| 6. A memory comprising a plurality of memory banks with a respective multiplicity of memory cells, wherein a command issuer
supplies request commands for reading data packets from memory cells which are selected before each request command by an
address information item, each memory bank comprising:
a sampling circuit arranged at a data output of an operating section and operated by sampling edges, wherein data packets
appear at the data output in response to a sequence of request commands, and
a control section configured to produce the sampling edges, the control section comprising at least two transmission branches
each comprising a copy of the operating section,
wherein pulse trains are applied to the transmission branches which have the same waveform as the sequence of request commands
and are delayed relative to one another, wherein the first pulse train is contemporaneous with the sequence of request commands,
and
wherein the sampling edges are produced from leading edges of the pulse trains which appear at the outputs of the transmission
branches.
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