| US 7,573,746 B1 | ||
| Volatile data storage in a non-volatile memory cell array | ||
| Jonathan Greene, Palo Alto, Calif. (US); and Robert M. Salter, III, Saratoga, Calif. (US) | ||
| Assigned to Actel Corporation, Mountain View, Calif. (US) | ||
| Filed on Sep. 26, 2007, as Appl. No. 11/861,504. | ||
| Application 11/861504 is a continuation of application No. 11/251074, filed on Oct. 13, 2005, granted, now 7,301,821. | ||
| Int. Cl. G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.18 [365/185.05; 365/185.1; 365/185.26; 365/185.33; 365/185.25] | 19 Claims |
| 1. An integrated circuit device capable of storing volatile data on common nodes in memory cells of a non-volatile memory
cell array comprising:
a non-volatile memory cell array comprising:
column lines;
row lines; and
a plurality of memory cells arranged in rows and columns and coupled to the row lines and the column lines, each memory cell
comprising a non-volatile device and a pull-up device connected at a common node;
a means for setting the non-volatile devices of each of the memory cells to a desired state;
a means for loading volatile data onto column lines of the non-volatile memory cell array;
a means for biasing non-volatile devices in the memory cells of the non-volatile memory cell array to store volatile data
from said column lines on the common nodes in the memory cells of the non-volatile memory cell array; and
a means for biasing pull-up devices and non-volatile devices in a first set of rows of the non-volatile memory cell array
to an off state;
wherein said means for biasing non-volatile devices in the memory cells of the non-volatile memory cell array is directed
towards a second set of rows of the non-volatile memory cell array.
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