| US 7,573,744 B2 | ||
| Semiconductor memory device having different capacity areas | ||
| Toshiaki Edahiro, Yokohama (Japan); Toshihiro Suzuki, Kawasaki (Japan); and Haruki Toda, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Sep. 28, 2007, as Appl. No. 11/864,089. | ||
| Claims priority of application No. 2006-266145 (JP), filed on Sep. 29, 2006. | ||
| Prior Publication US 2008/0080243 A1, Apr. 03, 2008 | ||
| Int. Cl. G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.17 [365/185.11] | 17 Claims |
| 1. A semiconductor memory device with NAND strings arranged therein, the NAND string having a plurality of electrically rewritable
and non-volatile memory cells connected in series, comprising:
a first data area; and
a second data area, which is smaller in capacity than the first data area and random accessible at a higher rate than the
first data area,
wherein
the first data area is sequentially accessed in such a way that a sector defined by a certain number of bits serves as an
access unit, and
the second data area has a word line length shorter than that of the first data area.
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