| US 7,573,735 B2 | ||
| Systems and methods for improving memory reliability | ||
| Satoru Takase, Austin, Tex. (US); and Takehito Sasaki, Austin, Tex. (US) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Sep. 08, 2006, as Appl. No. 11/530,271. | ||
| Prior Publication US 2008/0062747 A1, Mar. 13, 2008 | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—154 [365/189.06; 365/189.2; 365/196; 365/210.12] | 18 Claims |
| 1. A system comprising:
one or more logic components configured to receive power at a first voltage;
one or more memory cells configured to receive power at a second voltage; and
a critical condition detector configured to monitor the first and second voltages and to determine whether the first and second
voltages are within an acceptable range;
wherein the system is configured to inhibit accesses to the memory cells when the critical condition detector determines that
the first and second voltages are not within the acceptable range,
wherein the logic components comprise a processor and the memory cells comprise SRAM cells implemented on an integrated circuit
die with the processor; and
wherein the system is configured to inhibit accesses to the SRAM cells by stalling an instruction processing pipeline in the
processor.
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