| US 7,573,417 B2 | ||
| Multi-bit per stage pipelined analog to digital converters | ||
| James A. Bailey, Snowflake, Ariz. (US); and Mingdeng Chen, Cupertino, Calif. (US) | ||
| Assigned to Agere Systems Inc., Allentown, Pa. (US) | ||
| Filed on Feb. 05, 2008, as Appl. No. 12/25,914. | ||
| Claims priority of provisional application 60/989404, filed on Nov. 20, 2007. | ||
| Prior Publication US 2009/0128389 A1, May 21, 2009 | ||
| Int. Cl. H03M 1/38 (2006.01) | ||
| U.S. Cl. 341—161 [341/155] | 20 Claims |
| 1. A pipelined analog to digital converter, wherein the pipelined analog to digital converter comprises:
an analog to digital converter stage, wherein the analog to digital converter stage includes:
a multi-bit analog to digital converter, wherein the multi-bit analog to digital converter includes a particular number of
comparators; and
a digital to analog converter, wherein the digital to analog converter is controlled by outputs from the particular number
of comparators, wherein the digital to analog converter includes a residue amplifier with a feedback capacitance and an input
capacitance, and wherein the input capacitance includes the particular number of input capacitors; and
wherein the resolution of the analog to digital converter stage is selected to reduce the number of capacitor units.
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