| US 7,573,415 B1 | ||
| Area and power efficient analog to digital converter and methods for using such | ||
| James A. Bailey, Snowflake, Ariz. (US) | ||
| Assigned to Agere Systems Inc., Allentown, Pa. (US) | ||
| Filed on Feb. 01, 2008, as Appl. No. 12/24,893. | ||
| Int. Cl. H03M 1/12 (2006.01) | ||
| U.S. Cl. 341—155 [341/156] | 23 Claims |
| 1. An analog to digital converter circuit, the analog to digital converter circuit comprising:
a first comparator, wherein the first comparator receives an input voltage and a first reference voltage;
a first storage device, wherein the first storage device is electrically coupled to the first reference voltage;
a second comparator, wherein the second comparator receives the input voltage and a second reference voltage;
a second storage device, wherein the second storage device is electrically coupled to the second reference voltage; and
a reference voltage generation circuit, wherein the reference voltage generation circuit provides the first reference voltage
and the second reference voltage, wherein the first reference voltage is provided during a first time period and the second
reference voltage is provided during a second time period, and wherein the reference voltage generation circuit includes:
a digital to analog converter and a sequencer circuit, wherein the sequencer circuit causes a first digital value corresponding
to the first reference voltage to be applied to the digital to analog converter during the first time period, and wherein
the sequencer circuit causes a second digital value corresponding to the second reference voltage to be applied to the digital
to analog converter during the second time period.
|