| US 7,573,317 B2 | ||
| Apparatus and methods for adjusting performance of integrated circuits | ||
| David Lewis, Toronto (Canada); Vaughn Betz, Toronto (Canada); Irfan Rahim, San Jose, Calif. (US); Peter McElheny, Morgan Hill, Calif. (US); Yow-Juang W. Liu, San Jose, Calif. (US); and Bruce Pedersen, Sunnyvale, Calif. (US) | ||
| Assigned to Altera Corporation, San Jose, Calif. (US) | ||
| Filed on Sep. 26, 2006, as Appl. No. 11/535,065. | ||
| Application 11/535065 is a division of application No. 10/865402, filed on Jun. 10, 2004, granted, now 7,129,745. | ||
| Application 10/865402 is a continuation in part of application No. 10/848953, filed on May 19, 2004, granted, now 7,348,827. | ||
| Prior Publication US 2007/0069764 A1, Mar. 29, 2007 | ||
| Int. Cl. H03K 3/01 (2006.01) | ||
| U.S. Cl. 327—534 [327/530; 327/537] | 28 Claims |
| 1. A programmable logic device (PLD), comprising:
a reference transistor, the reference transistor configured to provide a current related to a circuit in the programmable
logic device (PLD);
a current measurement circuit, the measurement circuit configured to measure the current provided by the reference transistor
to provide a measured current signal; and
a body-bias generator, the body-bias generator configured to derive at least one body-bias signal from the measured current
signal, the body-bias generator further configured to provide the at least one body-bias signal to the circuit in the programmable
logic device (PLD).
|